Experiment 1 (Quartus II Familiarization)

I. Introduction:

                The group not so familiar to the Quartus II and they should know that is Quartus II all about. First are the components of this board. First is LED ( light emitting diode) and the switch. Quartus II Analysis and Synthesis, together with the Quartus II Fitter, incrementally compiles only the parts of your design that change between compilations. By compiling only changed partitions, incremental compilation reduces compilation time by up to 70 percent and it design software is a multiplatform design environment that easily adapts to your specific needs in all phases of FPGA and CPLD design. Quartus II software delivers the highest productivity and performance for Altera FPGAs, CPLDs, and HardCopy® ASICs.

II. Objective:

                To be able to create a logic circuit design in Quartus II

III. Conceptual Framework:

IV. Data and Results

DECODER

MULTIPLEXER

Results:

  The group set the seven segments into a pin codes then the output should be 0 to 9 then 10 to 15. A=10 B=11, C=12, D=13, E=14 and F=15. In multiplexer, the output should be in the switch the pin codes should be count 1 to 15 also like in the decoder.

V. Analysis:

  Given the seven segment in laboratory, our group analyze and discuss about the seven segment using the altera II or Quartus II by using the DE board and the gates that we use in the circuit of the diagram of the decoder and multiplexer. We able to finished the laboratory by helping of our professor.

VI. Conclusion:

   We therefore conclude that the Quartus II design software provides a complete design environment that you can easily adapt to your design for the development of Altera FPGAs, CPLDs, and HardCopy ASIC devices.