Experiment 2 (VHDL Familiarization)

I. Introduction:

                First the group is so familiar to the seven segment in the first experiment next Is the VHDL codes the program that we will use in the next experiment we should familiarize ourselves to make our work so familiar and good in the program of VHDL. We should know the characteristics of VHDL Support of modular hierarchical design.  Separate interface and body specifications of design entities. Multiple body specifications sharing the same interface (different levels of abstraction, alternatives, and versions). Late binding of bodies to entities using configurations.  Parameterized behavioral, structural and mixed descriptions. VHDL Common Intermediate form for simplified CAD tool access.

II. Objective:

                To be able to implement logic circuit design in VHDL codes

III. Conceptual Framework:

DIAGRAM OF DECODER:

DIAGRAM OF MULTIPLEXER

IV. Data and Results

                DECODER

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

entity dec is

port (

        bcd : in std_logic_vector(3 downto 0); 

        F : out std_logic_vector(6 downto 0) 

    );

end dec;

architecture DEC1 of dec is

begin

process (bcd)

begin

case  bcd is

when "0000" => F<="0000001";

when "0001" => F<="1001111";

when "0010" => F<="0010010";

when "0011" => F<="0000110";

when "0100" => F<="1001100";

when "0101" => F<="0100100";

when "0110" => F<="0100000";

when "0111" => F<="0001111";

when "1000" => F<="0000000";

when "1001" => F<="0000100";

when "1010" => F<="0001000";

when "1011" => F<="1100000";

when "1100" => F<="1110010";

when "1101" => F<="1000010";

when "1110" => F<="0010000";

when "1111" => F<="0111000";

end case;

end process;

end DEC1;

Multiplexer

use ieee.std_logic_1164.all;

entity Mux is

port (A,B : in bit_vector (3 downto 0);

O : out bit);

end entity;

architecture comp of Mux is

begin

process (A,B)

begin

if (A(3) = '1' AND B(3) = '0') then O <='1';

elsif (A(2) = '1' AND B(2) = '0') then O <='1';

elsif (A(1) = '1' AND B(1) = '0') then O <='1';

elsif (A(0) = '1' AND B(0) = '0') then O <='1';

else

O <= '0';

end if;

end process;

end comp;

Results:

   Like in the first experiment the DE board will set the output of 1 to 15 which A=10, B=11 , C=12, D=13, E=14 and F=15. Then next is the multiplexer the output of this is same in the first multiplexer. When you tap the switch the output is the same.

V. Analysis:

                We analyze and discuss about the meaning of the VHDL codes in this codes the we should program the codes of the decoder and multiplexer using the entity and architecture it includes of the codes we will use to make the program run. We compare the output of the A and the output B in the program.

VI. Conclusion:

                We learned that the program of the VHDL codes is quite so hard than to the gates that we use in the first experiment then the VHDL codes is quite hard but we able to finished the experiment in time.